An IC tester for testing semiconductor devices (generally, ICs, i.e., semiconductor integrated circuits) usually employs an IC handler integrally incorporated therein for transporting IC carriers loaded with ICs under test or trays carrying thereon IC carriers loaded with ICs under test from a loader section to a testing zone, and upon the test being completed, transporting them from the testing zone to an unloader section where the tested ICs are sorted into corresponding categories based on the data of the test results.
An example of the prior art IC handler called "forced horizontal transporting system" is shown in the form of a flow chart in FIG. 1. The IC handler 10 comprises a loader section 11 where ICs 15 under test carried on a customer (user) tray 13 are transferred and reloaded onto a test tray 14 capable of withstanding high/low temperatures, an unloader section 12 where tested ICs 15 are sorted, transferred and reloaded on customer trays 13 from a test tray 14, and a constant temperature chamber 20 including a testing zone 21 for receiving and testing the ICs from the loader section 11. The test trays 14 are moved in a circulating manner from and back to the loader section 11 sequentially through the constant temperature chamber 20 and the unloader section 12. More specifically, the test tray 14 loaded with ICs 15 to be tested is transported from the loader section 11 to a soak chamber 22 within the constant temperature chamber 20 where the ICs 15 on the test tray 14 are heated or cooled to a predetermined constant temperature. Generally, the soak chamber 22 is adapted to store a plurality of (say, ten) test trays 14 stacked one on another such that a test tray 14 newly received from the loader section 11 is stored at the bottom of the stack while the uppermost test tray is carried to the testing zone 21. The ICs 15 to be tested are heated or cooled to a predetermined constant temperature while the test tray 14 is moved from the bottom to the top of the stack within the soak chamber 22, and the heated or cooled ICs 15 together with the test tray 14 having the heated or cooled ICs 15 loaded are then transported while maintained at the constant temperature from the soak chamber 22 to the testing zone 21 where each of the ICs under test is brought into electrical contact with an IC socket (not shown) disposed in the testing zone 21 and electric characteristics of the ICs are measured. Upon completion of the test, the ICs 15 together with the test tray 14 are transported from the testing zone 21 to an exit chamber 23 where they are restored to the ambient temperature. Like the soak chamber 22, the exit chamber 23 is also adapted to store test trays in the form of a stack. In one embodiment the ICs 15 under test may be brought back to the ambient temperature as the associated test tray is moved sequentially from the top to the bottom of the stack within the exit chamber 23. Thereafter, the ICs 15 under test as carried on the test tray 14 are passed to the unloader section 12 where the tested ICs are sorted into categories based on the data of the test results and transferred from the test tray 14 onto the corresponding customer trays 13. The test tray 14 emptied in the unloader section 12 is delivered back to the loader section 11 where it is again loaded with ICs 15 to be tested from the customer tray 13 to repeat the same steps of operation. It is to be noted that the transfer of ICs 15 under test between the customer tray 13 and the test tray 14 is typically effected by suction transport means utilizing a vacuum pump which may pick up one to several ICs at a time for the transfer.
While the IC handler 10 illustrated in FIG. 1 is of the type which is configured to transport ICs under test together with the tray on which the ICs are loaded, IC handlers of the type adapted to transport ICs under test individually are also currently used.
As described above, an IC under test as loaded on the IC carrier is transported by the IC handler 10 from the loader section 11 to the testing zone 21 whence upon completion of the test they are passed to the unloader section 12. It should here be pointed out that surface mounting type ICs received in flat packages each of which has two arrays of leads extending from opposite sides thereof (flat package type ICs) as represented by the SOP (small outline package) and TSOP (thin small outline package) are tested for their electric characteristics in the testing zone by that each of the ICs is electrically connected with an IC socket as it is carried on an IC carrier. There are a variety of flat package type ICs with respect to the inter-lead array spacing (which refers to the spacing between two arrays of lead pins here in this specification), the number of pins, and the inter-pin spacing (which refers here to the spacing between adjacent lead pins in the lead pin array). To handle ICs of such various types of pin arrangement for electric testing, the IC handler has to exchange all IC carriers used for ICs of one specified type for IC carriers dedicated to Ics of another specified type whenever the inter-lead array spacing, the number of pins and/or the inter-pin spacing of the IC to be tested are varied. Moreover, with an increase in the integration density (higher the density of integration) of IC, the number of leads protruding from an IC package is increased with a decrease in the pin spacing (reduction in the pin pitch). To take one example, an IC having the inter-pin spacing of 0.5 mm has so small an inter-lead gap (gap between opposed edges of two adjacent lead pins) as about 0.2 mm (because each of the lead pins has a thickness or width of about 0.3 mm).
A typical example of the conventional IC carrier is illustrated in FIGS. 2-4. As shown in FIG. 2, the IC carrier 30 comprises a box-like housing 31 which has a generally rectangular shape in plan and is open in the top thereof. A flat package type IC is accommodated within the box-like housing 31. Formed in the bottom wall of the box-like housing 31 are two rows of contact holes 32 corresponding to the inter-lead array spacing, the inter-pin spacing and the number of pins of the flat package type IC to be housed. The contact holes 32 of each row are defined by thin plate carrier guides 33 two more than the number of leads of the flat package type IC to be accommodated, the carrier guides being spaced apart at predetermined intervals. As seen in FIGS. 3 and 4, these carrier guides 33 are positioned to project upwardly by a predetermined distance above the plane of the bottom floor of the housing 31, and the transverse dimension (width) of the flat package type IC (the distance between the two opposed sides of IC from which the leads protrude) is accommodated between the opposed side walls defined by the two rows of carrier guides 33 whereby the transverse (width-wise) movement of the flat package type IC is constrained, that is, the transverse position of the flat package type IC is determined in the housing. Alternatively, separate carrier guides having a positioning function which serves to transversely locate a flat package type IC to be received may be provided, and both the carrier guides 33 and the separate carrier guide may be used. The longitudinal dimension (length) of the bottom floor of the housing 31 is sized so as to correspond to the longitudinal dimension of the flat package type IC (the distance between the two opposed sides of IC from which no leads protrude) to thereby determine the longitudinal position of the flat package type IC in the housing. It is to be noted that the side walls of the housing 31 are tapered as illustrated to facilitate the insertion of the flat package type IC.
All of the rectangular housings 31 in all types of IC carrier have their exterior structures of the same shape and same size so that they can utilize the transport mechanism in the IC handler in common whereas the interior structures there of vary from one to another IC carrier so as to accommodate various flat package type ICs differing in the exterior configuration and the number of pins. It is for this reason that whenever the inter-lead array spacing, the number of pins and/or the inter-pin spacing of the flat package type IC to be tested are changed, the IC handler exchanges one type of IC carrier for another having a corresponding proper construction. A great number of, say 50 to 200 such IC carriers 30 are used in an IC handler.
The contact holes 32 are provided to permit the electrical testing to be effected on the IC under test while it is loaded on the IC carrier 30 in the testing zone 21. As illustrated in FIG. 5, when an IC (flat package type IC) 40 under test is deposited on the IC carrier 30, the IC leads 41 thereof are guided by the carrier guides 33 to overlie the corresponding contact holes 32. It is thus to be understood that the carrier guides 33 not only act as positioning guides to guide the IC leads 41 of the IC 40 under test into the respective contact holes 32, but also serve to prevent any lateral displacement of the IC leads 41 and short-circuit between adjacent IC leads as the upper end portions of the carrier guides 33 are interposed into respective gaps between adjacent IC leads 41.
The IC socket 50 for use in the electric testing in the testing zone 21 is provided with two rows of socket terminals (contacts) 51 spaced apart by the same distance as the spacing between the two rows of carrier guides 33, the socket terminals 51 of each row being of the same number and same pitch as the carrier guides 33 of the corresponding row. When the electric testing is to be carried out, the socket terminals 51 are inserted into the respective contact holes 32 of the IC carrier 30. During the test an IC lead hold-down mechanism 60 presses on the leads 41 of the IC 40 under test, as illustrated in FIG. 6, in order to insure electric contact between the leads 41 and the respective socket terminals 51 inserted into the contact holes 32. The IC lead hold-down mechanism 60 comprises a pair of insulative comb-like push members 61 having fingers equal in number and pitch to the leads 41 of the IC 40 under test, the arrangement being such that the fingers of each of the push members 61 will push down on the horizontally out-turned outer end portions of the corresponding leads 41 of the IC 40 under test to insure the electric contact with the socket terminals 51 in the contact holes 32.
As indicated above, with a recent enhancement in the integration density of IC, the more and more leads does the IC package have protruding therefrom with a corresponding decrease in the pin spacing. There have been evolved numerous ICs having an inter-lead gap (gap between opposed edges of two adjacent lead pins of each lead pin array of an IC) narrower than 0.2 mm. It follows that the thickness of the carrier guides 33 constituting partition walls for separating the contact holes 32 of the IC carrier 30 from each other must also be reduced to less than 0.2 mm, but it would be very difficult to fabricate such thin carrier guides. In addition, since the material of which the carrier guides 33 are made (normally molded integrally with the IC carrier 33) is an insulating material such as a plastic resin or the like, thin carrier guides are so weak in their strength, bringing forth the drawbacks that they may be broken when the IC under test is loaded on the IC carrier 30, that during the loading the IC leads 41 are apt to hit the carrier guides 33 to be bent thereby due to the reduced pitch between the pins, and that it takes a longer time to load the IC carrier with an IC.